1. Field of the Invention
The present invention relates to analog-to-digital conversion, and in particular relates to an Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC.
2. Description of the Related Art
Digital technology, especially computer technology, is a fast-growing and widely-adopted technology. In the control, communication, and testing fields, the processing of signals employs digital computing technology to a great extent. In practice, since the system typically works with certain analog signals such as temperature, pressure, motion displacement, or image, it is required to convert the analog signals into digital signals before various computing devices and digital apparatuses can recognize and process the signals. The circuit for converting an analog signal into a digital format is referred to as an Analog to Digital Converter (ADC).
FIG. 1 is a block diagram of a servo ADC (SV ADC) in the related art. A buffer is coupled to the input node of the ADC, and a multiplexer (MUX) outputs the output signal to the buffer amplifier. Since the input analog signal is continuous, and the output digital data are discrete, the ADC is required to sample the input analog signal at a selected sequence of instantaneous times, or certain predetermined points on the time axis, then convert the sampled values into output digital data DATA. Therefore a sample switch is required to be placed between the buffer and the ADC to provide the buffered signal in the buffer to the ADC as the input voltage for the analog-to-digital conversion.
FIG. 2 is a timing diagram for analog-to-digital conversion performed by the SV ADC in FIG. 1. As depicted in FIG. 2, the SV ADC requires 5T in time for completing the data sampling, and requires 11T in time for the conversion, wherein T is a clock cycle of the clock ck. After the conversion is completed, the ADC can release a ready signal, or a RDY signal, the falling edge of the RDY signal can serve as a flag signaling that the digital data DATA is ready. After 2T following the falling edge of the RDY signal, the MUX can switch the inputs, then in the following 9T, the buffer is in an idle state. Utilization of the idle state for the buffer can increase the efficiency of the analog-to-digital conversion.